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Ryan Schmidt (ryandesign) pushed a commit to branch master
in repository macports-ports.

</pre>
<p><a href="https://github.com/macports/macports-ports/commit/b72558716e56a88bd983a8f53f87cef815886ba6">https://github.com/macports/macports-ports/commit/b72558716e56a88bd983a8f53f87cef815886ba6</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'>     new b725587  vbpp: Use archived homepage and master_sites
</span>b725587 is described below

<span style='display:block; white-space:pre;color:#808000;'>commit b72558716e56a88bd983a8f53f87cef815886ba6
</span>Author: Ryan Schmidt <ryandesign@macports.org>
AuthorDate: Mon Oct 22 03:56:27 2018 -0500

<span style='display:block; white-space:pre;color:#404040;'>    vbpp: Use archived homepage and master_sites
</span><span style='display:block; white-space:pre;color:#404040;'>    
</span><span style='display:block; white-space:pre;color:#404040;'>    And modernize checksums.
</span>---
 science/vbpp/Portfile | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

<span style='display:block; white-space:pre;color:#808080;'>diff --git a/science/vbpp/Portfile b/science/vbpp/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index c05e084..8375b49 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/science/vbpp/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/science/vbpp/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -9,13 +9,14 @@ description         Verilog preprocessor
</span> long_description \
     VBPP is a Verilog preprocessor. It has support for most Verilog \
     preprocessing directives and additional directives.
<span style='display:block; white-space:pre;background:#ffe0e0;'>-homepage            http://www.verilog.net/free.html
</span> platforms           darwin
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-master_sites        http://www.verilog.net
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-checksums           md5     493ac8a83f92018649a0bdc50d65c24b \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                    sha1    79a05739977f98ab85678a7af16a189695dbd02d \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                    rmd160  177ee8bd4a3ea53f367f307476117de4bb7c1bb9
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+homepage            https://web.archive.org/web/20170425040737/http://www.verilog.net/free.html
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+master_sites        https://web.archive.org/web/20120205223616/http://www.verilog.net/
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums           rmd160  177ee8bd4a3ea53f367f307476117de4bb7c1bb9 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                    sha256  416c1bf9c4921fcb5fb4a9bef36f5c05e22e41d4099dc67aa9e636faeef78e16 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                    size    113047
</span> 
 use_parallel_build  no
 
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