<pre style='margin:0'>
Marcus Calhoun-Lopez (MarcusCalhoun-Lopez) pushed a commit to branch master
in repository macports-ports.
</pre>
<p><a href="https://github.com/macports/macports-ports/commit/5371ee3abb3794b36dccd4a8932b773b294abddd">https://github.com/macports/macports-ports/commit/5371ee3abb3794b36dccd4a8932b773b294abddd</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'> new 5371ee3 verilator: new port
</span>5371ee3 is described below
<span style='display:block; white-space:pre;color:#808000;'>commit 5371ee3abb3794b36dccd4a8932b773b294abddd
</span>Author: Marcus Calhoun-Lopez <mcalhoun@macports.org>
AuthorDate: Sat Jun 15 08:23:57 2019 -0700
<span style='display:block; white-space:pre;color:#404040;'> verilator: new port
</span><span style='display:block; white-space:pre;color:#404040;'>
</span><span style='display:block; white-space:pre;color:#404040;'> Fixes https://trac.macports.org/ticket/58606
</span>---
science/verilator/Portfile | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/science/verilator/Portfile b/science/verilator/Portfile
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 0000000..d792aba
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,30 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+PortSystem 1.0
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+PortGroup cxx11 1.1
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+name verilator
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+version 4.014
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+revision 0
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+categories science electronics
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+license {LGPL-3 Artistic-2}
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+maintainers {mcalhoun @MarcusCalhoun-Lopez} openmaintainer
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+platforms darwin
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+description Verilog compiler and simulator
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+long_description Verilator is a ${description}.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+homepage https://www.veripool.org/wiki/verilator
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+master_sites https://www.veripool.org/ftp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+extract.suffix .tgz
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums rmd160 9ee1c14dec7282f8ee9839f6fa5b9f57e00bce29 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ sha256 edf517b1b3ae0df98bd8d8189d17142c181cd50948d54a6ecb082f38804a33eb \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ size 2517003
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+installs_libs no
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+livecheck.type regex
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+livecheck.url https://www.veripool.org/projects/verilator/news
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+livecheck.regex "Verilator (\\d+(?:\\.\\d+)*) Released"
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