<pre style='margin:0'>
Renee Otten (reneeotten) pushed a commit to branch master
in repository macports-ports.
</pre>
<p><a href="https://github.com/macports/macports-ports/commit/59f103ba01ee8fa0e6bc23964be8dae7ed417df4">https://github.com/macports/macports-ports/commit/59f103ba01ee8fa0e6bc23964be8dae7ed417df4</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'> new 59f103ba01e logisim-evolution: update to 3.4.0
</span>59f103ba01e is described below
<span style='display:block; white-space:pre;color:#808000;'>commit 59f103ba01ee8fa0e6bc23964be8dae7ed417df4
</span>Author: harens <harensdeveloper@gmail.com>
AuthorDate: Wed Dec 23 10:33:38 2020 +0000
<span style='display:block; white-space:pre;color:#404040;'> logisim-evolution: update to 3.4.0
</span>---
cad/logisim-evolution/Portfile | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/cad/logisim-evolution/Portfile b/cad/logisim-evolution/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index c727fcf2c16..83c728cb0a6 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/cad/logisim-evolution/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/cad/logisim-evolution/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -4,7 +4,7 @@ PortSystem 1.0
</span> PortGroup java 1.0
PortGroup github 1.0
<span style='display:block; white-space:pre;background:#ffe0e0;'>-github.setup reds-heig logisim-evolution 3.3.6 v
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+github.setup reds-heig logisim-evolution 3.4.0 v
</span> revision 0
categories cad education java
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -18,9 +18,9 @@ description Digital logic designer and simulator
</span> long_description Logisim is an educational tool for designing and \
simulating digital logic circuits.
<span style='display:block; white-space:pre;background:#ffe0e0;'>-checksums rmd160 2f16261e7414be7fc6947f66271cddb3c5d2e2cb \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- sha256 06344fbf4c6a5f8d0809aecba7a0e7ce790e8e9ef24e69874e7f52c6b2d1424f \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- size 39941718
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums rmd160 edf94f1ff9943799439c423fe2141055be25b5dd \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ sha256 c3ed59dc72e5985659128821c9d1e2a63cd118142604649d04a4447c7cea0b07 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ size 39945795
</span>
java.version 1.8+
java.fallback openjdk10
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