<pre style='margin:0'>
Chris Jones (cjones051073) pushed a commit to branch master
in repository macports-ports.
</pre>
<p><a href="https://github.com/macports/macports-ports/commit/28431a6f25e07ebacaaf42ed3c3e1abfe8e98e64">https://github.com/macports/macports-ports/commit/28431a6f25e07ebacaaf42ed3c3e1abfe8e98e64</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'> new 28431a6f25e ispc: Update to 1.15.0, LLVM 11.0.0
</span>28431a6f25e is described below
<span style='display:block; white-space:pre;color:#808000;'>commit 28431a6f25e07ebacaaf42ed3c3e1abfe8e98e64
</span>Author: Chris Jones <jonesc@macports.org>
AuthorDate: Thu Apr 15 12:01:11 2021 +0100
<span style='display:block; white-space:pre;color:#404040;'> ispc: Update to 1.15.0, LLVM 11.0.0
</span>---
lang/ispc/Portfile | 36 +++++----
.../11_0_11_1_disable-A-B-A-B-in-InstCombine.patch | 34 +++++++++
.../files/11_0_11_1_packed_load_store_avx512.patch | 86 ++++++++++++++++++++++
3 files changed, 143 insertions(+), 13 deletions(-)
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/Portfile b/lang/ispc/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index 243925de922..f709effeaea 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/lang/ispc/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -19,13 +19,15 @@ platforms darwin
</span> supported_archs x86_64
maintainers {takeshi @tenomoto} openmaintainer
<span style='display:block; white-space:pre;background:#e0ffe0;'>+# For build instructions see https://github.com/ispc/ispc/wiki/Building-ispc
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span> if { ${subport} eq ${name} } {
<span style='display:block; white-space:pre;background:#ffe0e0;'>- github.setup ispc ispc 1.14.1 v
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ github.setup ispc ispc 1.15.0 v
</span>
<span style='display:block; white-space:pre;background:#ffe0e0;'>- checksums rmd160 f56581854e80e099d328c74c79dad2d77158f3e5 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- sha256 ca12f26dafbc4ef9605487d03a2156331c1351a4ffefc9bab4d896a466880794 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- size 19454277
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ checksums rmd160 b3e07e252a37c28261209d2159d34c0505de22e9 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ sha256 3b634aaa10c9bf0e82505d1af69cb307a3a00182d57eae019680ccfa62338af9 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ size 19497873
</span>
license BSD
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -33,7 +35,7 @@ if { ${subport} eq ${name} } {
</span> long_description ${name} is a compiler for a variant of the C programming language, \
with extensions for single program, multiple data programming.
<span style='display:block; white-space:pre;background:#ffe0e0;'>- set py_ver 3.8
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ set py_ver 3.9
</span> set py_ver_nodot [string map {. {}} ${py_ver}]
depends_build-append port:bison \
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -85,16 +87,17 @@ if { ${subport} eq ${name} } {
</span>
subport ispc-clang {
<span style='display:block; white-space:pre;background:#ffe0e0;'>- github.setup llvm llvm-project 10.0.1 llvmorg-
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ # Note - ispc currently has issues with LLVM 11.1.0 so skip for now.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ github.setup llvm llvm-project 11.0.0 llvmorg-
</span>
<span style='display:block; white-space:pre;background:#ffe0e0;'>- checksums rmd160 6368fe23eec894cf34bf3d894ce4e4538383084e \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- sha256 b53a262e7598c47fae7315d957429757dd8f341d3492793e77cbe6b4b6c0c931 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- size 120879075
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ checksums rmd160 43f9b90bfee998e51629993ecef378b981c7bada \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ sha256 d76bf03273a5a1c1168413e93071693be4509880a695665d97a8a70762e8a88b \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ size 122764036
</span>
license NCSA
description Clang build specifically for ispc compiler.
<span style='display:block; white-space:pre;background:#ffe0e0;'>- long_description ${description} NOT TO BE USED IN GENERAL. This build is specifically tuned \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ long_description {*}${description} NOT TO BE USED IN GENERAL. This build is specifically tuned \
</span> to satisfy the requirements of ispc which uses it as a build dependency only. \
Has assertions and dump enabled by default, which is not the case in the \
primary MacPorts LLVM/Clang builds.
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -103,13 +106,18 @@ subport ispc-clang {
</span> # then simplified and adapted for usage here
patchfiles patch-compilerrtdarwinutils-find-macosxsdkversion.diff
<span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ # From https://github.com/ispc/ispc/tree/main/llvm_patches
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ patchfiles-append 11_0_11_1_packed_load_store_avx512.patch \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ 11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
</span>
<span style='display:block; white-space:pre;background:#ffe0e0;'>- set py_ver 2.7
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ set py_ver 3.9
</span> set py_ver_nodot [string map {. {}} ${py_ver}]
depends_lib-append port:libedit \
<span style='display:block; white-space:pre;background:#ffe0e0;'>- port:ncurses port:z3 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ port:ncurses \
</span> path:lib/libxar.dylib:xar \
<span style='display:block; white-space:pre;background:#e0ffe0;'>+ port:z3 \
</span> port:zlib \
port:libxml2 \
port:libomp \
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -135,7 +143,8 @@ subport ispc-clang {
</span> configure.args-replace -DCMAKE_SYSTEM_PREFIX_PATH="${prefix}\;/usr" \
-DCMAKE_SYSTEM_PREFIX_PATH="${cmake.install_prefix}\;${prefix}\;/usr"
<span style='display:block; white-space:pre;background:#ffe0e0;'>- configure.args-append -DLLVM_ENABLE_PROJECTS="clang\;libcxx\;compiler-rt" \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ configure.args-append -DLLVM_ENABLE_PROJECTS="clang" \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ -DLLVM_TARGETS_TO_BUILD="AArch64\;ARM\;X86" \
</span> -DLLVM_LINK_LLVM_DYLIB=ON \
-DLLVM_ENABLE_ASSERTIONS=ON \
-DLLVM_ENABLE_DUMP=ON \
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -153,6 +162,7 @@ subport ispc-clang {
</span> -DLIBCXX_ENABLE_SHARED=OFF \
-DLIBCXX_INSTALL_LIBRARY=OFF \
-DCOMPILER_RT_BUILD_SANITIZERS=OFF \
<span style='display:block; white-space:pre;background:#e0ffe0;'>+ -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=WebAssembly \
</span> -DPYTHON_EXECUTABLE=${prefix}/bin/python${py_ver}
livecheck.url https://github.com/llvm/llvm-project/releases
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch b/lang/ispc/files/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..2f42f1f07ee
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/files/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,34 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# This patch is needed for ISPC for Gen only
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# Transformation of add to or is not safe for VC backend.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index a7f5e0a7774d..bf02b0f70827 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -15,6 +15,7 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #include "llvm/ADT/APInt.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #include "llvm/ADT/STLExtras.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #include "llvm/ADT/SmallVector.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#include "llvm/ADT/Triple.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #include "llvm/Analysis/InstructionSimplify.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #include "llvm/Analysis/ValueTracking.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #include "llvm/IR/Constant.h"
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -1324,10 +1325,13 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return BinaryOperator::CreateSRem(RHS, NewRHS);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+-
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- // A+B --> A|B iff A and B have no bits set in common.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- return BinaryOperator::CreateOr(LHS, RHS);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // Disable this transformation for ISPC SPIR-V
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // A+B --> A|B iff A and B have no bits set in common.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return BinaryOperator::CreateOr(LHS, RHS);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // FIXME: We already did a check for ConstantInt RHS above this.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // FIXME: Is this pattern covered by another fold? No regression tests fail on
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/11_0_11_1_packed_load_store_avx512.patch b/lang/ispc/files/11_0_11_1_packed_load_store_avx512.patch
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..ac8b6648607
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/files/11_0_11_1_packed_load_store_avx512.patch
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,86 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# This patch is required for llvm.expandload/compressstore intrinsiscs to work
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# correctly for i64 types on avx512skx-i32x8
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Commit a4124e455e641db1e18d4221d2dacb31953fd13b Mon Sep 17 00:00:00 2001
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Author: Craig Topper <craig.topper@sifive.com>
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Date: Thu, 12 Nov 2020 20:18:50 -0800
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Subject: [X86] When storing v1i1/v2i1/v4i1 to memory, make sure we store zeros
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ in the rest of the byte
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+We can't store garbage in the unused bits. It possible that something like zextload from i1/i2/i4 is created to read the memory. Those zextloads would be legalized assuming the extra bits are 0.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+I'm not sure that the code in lowerStore is executed for the v1i1/v2i1/v4i1 case. It looks like the DAG combine in combineStore may have converted them to v8i1 first. And I think we're missing some cases to avoid going to the stack in the first place. But I don't have time to investigate those things at the moment so I wanted to focus on the correctness issue.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Should fix PR48147.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Reviewed By: RKSimon
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+Differential Revision: https://reviews.llvm.org/D91294
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 5b0e9fa7535..f1956d77d61 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Target/X86/X86ISelLowering.cpp.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Target/X86/X86ISelLowering.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -23870,17 +23870,22 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Without AVX512DQ, we need to use a scalar type for v2i1/v4i1/v8i1 stores.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ if (StoredVal.getValueType().isVector() &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal.getValueType().getVectorElementType() == MVT::i1) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- assert(StoredVal.getValueType().getVectorNumElements() <= 8 &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- "Unexpected VT");
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ unsigned NumElts = StoredVal.getValueType().getVectorNumElements();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ assert(NumElts <= 8 && "Unexpected VT");
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ assert(!St->isTruncatingStore() && "Expected non-truncating store");
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ assert(Subtarget.hasAVX512() && !Subtarget.hasDQI() &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ "Expected AVX512F without AVX512DQI");
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // We must pad with zeros to ensure we store zeroes to any unused bits.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ DAG.getUNDEF(MVT::v16i1), StoredVal,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ DAG.getIntPtrConstant(0, dl));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal = DAG.getBitcast(MVT::i16, StoredVal);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, StoredVal);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // Make sure we store zeros in the extra bits.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (NumElts < 8)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ StoredVal = DAG.getZeroExtendInReg(StoredVal, dl,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ MVT::getIntegerVT(NumElts));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ St->getPointerInfo(), St->getOriginalAlign(),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -44971,17 +44976,21 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal.getOpcode() == ISD::SCALAR_TO_VECTOR &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal.getOperand(0).getValueType() == MVT::i8) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- return DAG.getStore(St->getChain(), dl, StoredVal.getOperand(0),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Val = StoredVal.getOperand(0);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // We must store zeros to the unused bits.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return DAG.getStore(St->getChain(), dl, Val,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ St->getBasePtr(), St->getPointerInfo(),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ St->getOriginalAlign(),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ St->getMemOperand()->getFlags());
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Widen v2i1/v4i1 stores to v8i1.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- if ((VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ Subtarget.hasAVX512()) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ unsigned NumConcats = 8 / VT.getVectorNumElements();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- SmallVector<SDValue, 4> Ops(NumConcats, DAG.getUNDEF(VT));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // We must store zeros to the unused bits.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SmallVector<SDValue, 4> Ops(NumConcats, DAG.getConstant(0, dl, VT));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ Ops[0] = StoredVal;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 3d8fbdc3b82..339fd001643 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Target/X86/X86InstrAVX512.td.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Target/X86/X86InstrAVX512.td
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -2921,9 +2921,6 @@ def : Pat<(i64 (bitconvert (v64i1 VK64:$src))),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Load/store kreg
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ let Predicates = [HasDQI] in {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- def : Pat<(store VK1:$src, addr:$dst),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+-
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ def : Pat<(v1i1 (load addr:$src)),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ def : Pat<(v2i1 (load addr:$src)),
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