<pre style='margin:0'>
Marcus Calhoun-Lopez (MarcusCalhoun-Lopez) pushed a commit to branch master
in repository macports-ports.

</pre>
<p><a href="https://github.com/macports/macports-ports/commit/2b3da91a46af14a50f97583f78a1e5f60ba1c0f0">https://github.com/macports/macports-ports/commit/2b3da91a46af14a50f97583f78a1e5f60ba1c0f0</a></p>
<pre style="white-space: pre; background: #F8F8F8"><span style='display:block; white-space:pre;color:#808000;'>commit 2b3da91a46af14a50f97583f78a1e5f60ba1c0f0
</span>Author: Marcus Calhoun-Lopez <mcalhoun@macports.org>
AuthorDate: Sat Apr 24 08:47:40 2021 -0700

<span style='display:block; white-space:pre;color:#404040;'>    verilator: update version 4.104->4.202
</span>---
 science/verilator/Portfile | 25 +++++++++----------------
 1 file changed, 9 insertions(+), 16 deletions(-)

<span style='display:block; white-space:pre;color:#808080;'>diff --git a/science/verilator/Portfile b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index 8c87abd1027..032d1c5bf15 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -3,7 +3,7 @@
</span> PortSystem              1.0
 
 name                    verilator
<span style='display:block; white-space:pre;background:#ffe0e0;'>-version                 4.104
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+version                 4.202
</span> revision                0
 categories              science electronics
 license                 {LGPL-3 Artistic-2}
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -18,9 +18,9 @@ master_sites            https://www.veripool.org/ftp
</span> 
 extract.suffix          .tgz
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-checksums               rmd160  071de6ea17075b8f8563579ce54a34b9f150f0c0 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        sha256  3c65e11b6dbd8f3119ee580f404b6db733f57f7ba167e7140ba03371e489dd72 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        size    2784494
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums               rmd160  709fa1b70af80f23d6ada18098df8e7ab846d4ab \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        sha256  d8daff2461493439889f85e4a9ccb2d865e9c4ca1a06f611fe36d64bc020b679 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        size    3149226
</span> 
 compiler.cxx_standard   2014
 
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -35,18 +35,11 @@ configure.env-append    LEX=${prefix}/bin/flex
</span> depends_build-append    port:grep
 configure.env-append    GREP=${prefix}/bin/grep
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-#avoid
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#    In file included from ../V3ParseGrammar.cpp:22:
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#    verilog.c:686:40: warning: '/*' within block comment [-Wcomment]
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#        yVL_CLOCK = 610,               /* "/*verilator sc_clock*/"  */
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#                                           ^
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#    verilog.c:686:62: warning: missing terminating '"' character [-Winvalid-pp-token]
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#        yVL_CLOCK = 610,               /* "/*verilator sc_clock*/"  */
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#                                                                 ^
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#    verilog.c:686:62: error: expected identifier
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#depends_build-append    port:bison
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-#configure.env-append    YACC=${prefix}/bin/bison
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-configure.env-append    YACC=/usr/bin/bison
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+depends_build-append    port:bison
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+configure.env-append    YACC=${prefix}/bin/bison
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+depends_build-append    port:python39
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+configure.env-append    PYTHON3=${prefix}/bin/python3.9
</span> 
 livecheck.url           https://github.com/verilator/verilator/tags
 livecheck.regex         {/v(\d+(?:\.\d+)*)"}
</pre><pre style='margin:0'>

</pre>