<pre style='margin:0'>
Rainer Müller (raimue) pushed a commit to branch master
in repository macports-ports.
</pre>
<p><a href="https://github.com/macports/macports-ports/commit/a8146c789decbeccc92f994f84727532a354e2cf">https://github.com/macports/macports-ports/commit/a8146c789decbeccc92f994f84727532a354e2cf</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'> new a8146c789de qemu: fix linux guests on arm hvf
</span>a8146c789de is described below
<span style='display:block; white-space:pre;color:#808000;'>commit a8146c789decbeccc92f994f84727532a354e2cf
</span>Author: Albert Peschar <albert@peschar.net>
AuthorDate: Mon Apr 18 11:34:03 2022 +0300
<span style='display:block; white-space:pre;color:#404040;'> qemu: fix linux guests on arm hvf
</span>---
emulators/qemu/Portfile | 7 +-
emulators/qemu/files/patch-qemu-7f6c295.diff | 32 ++++++++
emulators/qemu/files/patch-qemu-ad99f64.diff | 107 +++++++++++++++++++++++++++
3 files changed, 145 insertions(+), 1 deletion(-)
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/emulators/qemu/Portfile b/emulators/qemu/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index 9f10c69e53a..c928556064a 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/emulators/qemu/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/emulators/qemu/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -9,7 +9,7 @@ legacysupport.newest_darwin_requires_legacy 15
</span>
name qemu
version 6.2.0
<span style='display:block; white-space:pre;background:#ffe0e0;'>-revision 0
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+revision 1
</span> categories emulators
license GPL-2+
platforms darwin
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -64,6 +64,11 @@ patchfiles-append patch-qemu-include-qemu-osdep.diff
</span> # MAP_JIT workaround
patchfiles-append patch-qemu-tcg-region.diff
<span style='display:block; white-space:pre;background:#e0ffe0;'>+# Backports from QEMU 7 which are necessary for newer Linux guests on ARM
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# See https://gitlab.com/qemu-project/qemu/-/issues/899
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+patchfiles-append patch-qemu-ad99f64.diff
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+patchfiles-append patch-qemu-7f6c295.diff
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span> # "ERROR: You need at least GCC v7.5 or Clang v6.0 (or XCode Clang v10.0)"
compiler.blacklist {clang < 1000} {macports-clang-[3-5].*} {macports-gcc-[56]} {*gcc-[34].*}
if {${os.platform} eq "darwin" && ${os.major} < 11 && [string match *clang* ${configure.compiler}]} {
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/emulators/qemu/files/patch-qemu-7f6c295.diff b/emulators/qemu/files/patch-qemu-7f6c295.diff
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..d9295077827
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/emulators/qemu/files/patch-qemu-7f6c295.diff
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,32 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git target/arm/hvf/hvf.c target/arm/hvf/hvf.c
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 808c96da8ccbd8d191f5b78ed397d39463aa3809..4d4ddab348a7d73c4c99ca18705dc3257aebfa8a 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- target/arm/hvf/hvf.c
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ target/arm/hvf/hvf.c
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -754,6 +754,15 @@ static bool hvf_handle_psci_call(CPUState *cpu)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return true;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++static bool is_id_sysreg(uint32_t reg)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++{
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return SYSREG_OP0(reg) == 3 &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP1(reg) == 0 &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRN(reg) == 0 &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM(reg) >= 1 &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM(reg) < 8;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++}
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ ARMCPU *arm_cpu = ARM_CPU(cpu);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -806,6 +815,11 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ /* Dummy register */
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ break;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ default:
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (is_id_sysreg(reg)) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ /* ID system registers read as RES0 */
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ val = 0;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ break;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ cpu_synchronize_state(cpu);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ trace_hvf_unhandled_sysreg_read(env->pc, reg,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ SYSREG_OP0(reg),
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/emulators/qemu/files/patch-qemu-ad99f64.diff b/emulators/qemu/files/patch-qemu-ad99f64.diff
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..1a53f3c4e8d
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/emulators/qemu/files/patch-qemu-ad99f64.diff
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,107 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git target/arm/hvf/hvf.c target/arm/hvf/hvf.c
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 0dc96560d3469316907f70efcc971b540687a570..808c96da8ccbd8d191f5b78ed397d39463aa3809 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- target/arm/hvf/hvf.c
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ target/arm/hvf/hvf.c
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -35,9 +35,34 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #define PL1_WRITE_MASK 0x4
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP0_SHIFT 20
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP0_MASK 0x3
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP1_SHIFT 14
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP1_MASK 0x7
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_CRN_SHIFT 10
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_CRN_MASK 0xf
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_CRM_SHIFT 1
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_CRM_MASK 0xf
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP2_SHIFT 17
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP2_MASK 0x7
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #define SYSREG(op0, op1, crn, crm, op2) \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+-#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ ((op0 << SYSREG_OP0_SHIFT) | \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ (op1 << SYSREG_OP1_SHIFT) | \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ (crn << SYSREG_CRN_SHIFT) | \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ (crm << SYSREG_CRM_SHIFT) | \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ (op2 << SYSREG_OP2_SHIFT))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++#define SYSREG_MASK \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG(SYSREG_OP0_MASK, \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP1_MASK, \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRN_MASK, \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM_MASK, \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP2_MASK)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -783,21 +808,21 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ default:
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ cpu_synchronize_state(cpu);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ trace_hvf_unhandled_sysreg_read(env->pc, reg,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 20) & 0x3,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 14) & 0x7,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 10) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 1) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 17) & 0x7);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP0(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP1(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRN(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP2(reg));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return 1;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ trace_hvf_sysreg_read(reg,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 20) & 0x3,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 14) & 0x7,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 10) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 1) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 17) & 0x7,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP0(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP1(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRN(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP2(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ val);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ hvf_set_reg(cpu, rt, val);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -886,11 +911,11 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ CPUARMState *env = &arm_cpu->env;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ trace_hvf_sysreg_write(reg,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 20) & 0x3,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 14) & 0x7,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 10) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 1) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 17) & 0x7,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP0(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP1(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRN(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP2(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ val);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ switch (reg) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -960,11 +985,11 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ default:
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ cpu_synchronize_state(cpu);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ trace_hvf_unhandled_sysreg_write(env->pc, reg,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 20) & 0x3,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 14) & 0x7,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 10) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 1) & 0xf,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- (reg >> 17) & 0x7);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP0(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP1(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRN(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_CRM(reg),
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SYSREG_OP2(reg));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return 1;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span></pre><pre style='margin:0'>
</pre>