<pre style='margin:0'>
Marcus Calhoun-Lopez (MarcusCalhoun-Lopez) pushed a commit to branch master
in repository macports-ports.

</pre>
<p><a href="https://github.com/macports/macports-ports/commit/8079eff90f0592296171dc0a8f18190ae0476abc">https://github.com/macports/macports-ports/commit/8079eff90f0592296171dc0a8f18190ae0476abc</a></p>
<pre style="white-space: pre; background: #F8F8F8"><span style='display:block; white-space:pre;color:#808000;'>commit 8079eff90f0592296171dc0a8f18190ae0476abc
</span>Author: Marcus Calhoun-Lopez <mcalhoun@macports.org>
AuthorDate: Tue Dec 27 06:56:00 2022 -0700

<span style='display:block; white-space:pre;color:#404040;'>    verilator: switch master site to GitHub
</span>---
 science/verilator/Portfile | 21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)

<span style='display:block; white-space:pre;color:#808080;'>diff --git a/science/verilator/Portfile b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index 959212aed94..9131957bf0a 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -1,9 +1,9 @@
</span> # -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4
 
 PortSystem              1.0
<span style='display:block; white-space:pre;background:#e0ffe0;'>+PortGroup               github 1.0
</span> 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-name                    verilator
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-version                 4.202
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+github.setup            verilator verilator 4.202 v
</span> revision                0
 categories              science electronics
 license                 {LGPL-3 Artistic-2}
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -12,18 +12,14 @@ platforms               darwin
</span> description             Verilog compiler and simulator
 long_description        Verilator is a {*}${description}.
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-homepage                https://www.veripool.org/wiki/verilator
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-master_sites            https://www.veripool.org/ftp
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-extract.suffix          .tgz
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-checksums               rmd160  709fa1b70af80f23d6ada18098df8e7ab846d4ab \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        sha256  d8daff2461493439889f85e4a9ccb2d865e9c4ca1a06f611fe36d64bc020b679 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        size    3149226
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums               rmd160  613bc0c4924245f128ff3845aabafb7dc98c6c12 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        sha256  53faa192b313779017ddc73537ecfd16d208ce5a12004a218842bdb9d414d550 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        size    2353074
</span> 
 compiler.cxx_standard   2014
 
<span style='display:block; white-space:pre;background:#e0ffe0;'>+use_autoconf            yes
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span> installs_libs           no
 
 depends_build-append    port:perl5.34
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -40,6 +36,3 @@ configure.env-append    YACC=${prefix}/bin/bison
</span> 
 depends_build-append    port:python310
 configure.env-append    PYTHON3=${prefix}/bin/python3.10
<span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-livecheck.url           https://github.com/verilator/verilator/tags
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-livecheck.regex         {/v(\d+(?:\.\d+)*)"}
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