<pre style='margin:0'>
Chris Jones (cjones051073) pushed a commit to branch master
in repository macports-ports.
</pre>
<p><a href="https://github.com/macports/macports-ports/commit/d31ed5c6c19a032630805e23039949b9524e5123">https://github.com/macports/macports-ports/commit/d31ed5c6c19a032630805e23039949b9524e5123</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'> new d31ed5c6c19 ispc: update to 1.19.0
</span>d31ed5c6c19 is described below
<span style='display:block; white-space:pre;color:#808000;'>commit d31ed5c6c19a032630805e23039949b9524e5123
</span>Author: Chris Jones <jonesc@macports.org>
AuthorDate: Tue Mar 7 11:04:58 2023 +0000
<span style='display:block; white-space:pre;color:#404040;'> ispc: update to 1.19.0
</span>---
lang/ispc/Portfile | 54 ++++++-----
.../11_0_11_1_disable-A-B-A-B-in-InstCombine.patch | 34 -------
.../files/11_0_11_1_packed_load_store_avx512.patch | 86 -----------------
.../14_0_15_0_disable-DIArgList-in-SPIR-V.patch | 25 +++++
lang/ispc/files/14_0_AVX512VP2INTERSECT.patch | 41 ++++++++
.../files/14_0_fp16_converts.partial.fix.patch | 104 +++++++++++++++++++++
lang/ispc/files/patch-CMakeLists.txt.diff | 17 ----
7 files changed, 200 insertions(+), 161 deletions(-)
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/Portfile b/lang/ispc/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index a7a38987417..41a5c8ba989 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/lang/ispc/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -19,16 +19,19 @@ platforms darwin
</span> supported_archs x86_64
maintainers nomaintainer
<span style='display:block; white-space:pre;background:#e0ffe0;'>+set py_ver 3.11
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+set py_ver_nodot [string map {. {}} ${py_ver}]
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span> # For build instructions see https://github.com/ispc/ispc/wiki/Building-ispc
if { ${subport} eq ${name} } {
<span style='display:block; white-space:pre;background:#ffe0e0;'>- github.setup ispc ispc 1.16.0 v
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- revision 1
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ github.setup ispc ispc 1.19.0 v
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ revision 0
</span>
<span style='display:block; white-space:pre;background:#ffe0e0;'>- checksums rmd160 28e97ce0d828c16e78d8f794a6c6f6fcebbbd830 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- sha256 12db1a90046b51752a65f50426e1d99051c6d55e30796ddd079f7bc97d5f6faf \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- size 19547681
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ checksums rmd160 90bb1d6aef518ef457114edcd84131a87a37f158 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ sha256 c1aeae4bdfb28004a6949394ea1b3daa3fdf12f646e17fcc0614861077dc8b6a \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ size 19578123
</span>
license BSD
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -36,9 +39,6 @@ if { ${subport} eq ${name} } {
</span> long_description ${name} is a compiler for a variant of the C programming language, \
with extensions for single program, multiple data programming.
<span style='display:block; white-space:pre;background:#ffe0e0;'>- set py_ver 3.9
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- set py_ver_nodot [string map {. {}} ${py_ver}]
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span> depends_build-append port:bison \
port:cctools \
port:flex \
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -46,9 +46,8 @@ if { ${subport} eq ${name} } {
</span> port:python${py_ver_nodot}
depends_lib-append port:ncurses \
<span style='display:block; white-space:pre;background:#ffe0e0;'>- port:zlib
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- patchfiles patch-CMakeLists.txt.diff
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ port:zlib \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ port:zstd
</span>
post-patch {
if {${os.platform} eq "darwin" && ${os.major} >= 18} {
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -63,7 +62,7 @@ if { ${subport} eq ${name} } {
</span> }
# Need to use a recent MacPorts build.
<span style='display:block; white-space:pre;background:#ffe0e0;'>- compiler.cxx_standard 2014
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ compiler.cxx_standard 2017
</span> compiler.blacklist *gcc* clang {macports-clang-[5-8].0} macports-clang-3.*
use_xcode yes
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -75,6 +74,11 @@ if { ${subport} eq ${name} } {
</span> -DLLVM_DIR=${prefix}/libexec/ispc-clang/lib/cmake/llvm \
-DISPC_INCLUDE_TESTS=OFF
<span style='display:block; white-space:pre;background:#e0ffe0;'>+ # Build has problems finding zlib
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ configure.ldflags-append ${prefix}/lib/libz.a
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ configure.args-append -DZLIB_INCLUDE_DIR=${prefix}/include \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ -DZLIB_LIBRARY=${prefix}/lib/libz.a
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span> test.run yes
test.dir ${worksrcpath}
test.cmd ./run_tests.py
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -86,12 +90,13 @@ if { ${subport} eq ${name} } {
</span>
subport ispc-clang {
<span style='display:block; white-space:pre;background:#ffe0e0;'>- # Note - ispc currently has issues with LLVM 11.1.0 so skip for now.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- github.setup llvm llvm-project 11.0.0 llvmorg-
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ # See ispc release notes for LLVM version each release is based on
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ # https://github.com/ispc/ispc/releases
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ github.setup llvm llvm-project 14.0.6 llvmorg-
</span>
<span style='display:block; white-space:pre;background:#ffe0e0;'>- checksums rmd160 43f9b90bfee998e51629993ecef378b981c7bada \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- sha256 d76bf03273a5a1c1168413e93071693be4509880a695665d97a8a70762e8a88b \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- size 122764036
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ checksums rmd160 1a92ac23507901e13fc26aea7dca33b8c6cb2d2c \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ sha256 8e9e1948974cdcd642793f1fe195369d13950623c47f27d4266396d3576e4f5b \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ size 158100103
</span>
license NCSA
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -107,17 +112,16 @@ subport ispc-clang {
</span> patchfiles patch-compilerrtdarwinutils-find-macosxsdkversion.diff
# From https://github.com/ispc/ispc/tree/main/llvm_patches
<span style='display:block; white-space:pre;background:#ffe0e0;'>- patchfiles-append 11_0_11_1_packed_load_store_avx512.patch \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- 11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- set py_ver 3.9
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- set py_ver_nodot [string map {. {}} ${py_ver}]
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ patchfiles-append 14_0_15_0_disable-DIArgList-in-SPIR-V.patch \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ 14_0_AVX512VP2INTERSECT.patch \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ 14_0_fp16_converts.partial.fix.patch
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span> depends_lib-append port:libedit \
port:ncurses \
path:lib/libxar.dylib:xar \
port:z3 \
port:zlib \
<span style='display:block; white-space:pre;background:#e0ffe0;'>+ port:zstd \
</span> port:libxml2 \
port:libomp \
bin:perl:perl5 \
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -127,7 +131,8 @@ subport ispc-clang {
</span> port:python${py_ver_nodot}
compiler.cxx_standard 2014
<span style='display:block; white-space:pre;background:#ffe0e0;'>- compiler.blacklist *gcc* {clang < 801} macports-clang-3.* {macports-clang-[4-8].0}
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ compiler.blacklist *gcc* {clang < 1204} macports-clang-3.* {macports-clang-[4-6].0} {macports-clang-1[0-2]}
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ compiler.fallback clang macports-clang-13 macports-clang-14
</span>
cmake.install_prefix ${prefix}/libexec/${subport}
cmake.build_type Release
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -161,6 +166,7 @@ subport ispc-clang {
</span> -DLIBCXX_ENABLE_SHARED=OFF \
-DLIBCXX_INSTALL_LIBRARY=OFF \
-DCOMPILER_RT_BUILD_SANITIZERS=OFF \
<span style='display:block; white-space:pre;background:#e0ffe0;'>+ -DCOMPILER_RT_ENABLE_IOS=OFF \
</span> -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=WebAssembly \
-DPYTHON_EXECUTABLE=${prefix}/bin/python${py_ver}
<span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch b/lang/ispc/files/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
</span>deleted file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 2f42f1f07ee..00000000000
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/lang/ispc/files/11_0_11_1_disable-A-B-A-B-in-InstCombine.patch
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -1,34 +0,0 @@
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-# This patch is needed for ISPC for Gen only
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-# Transformation of add to or is not safe for VC backend.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-index a7f5e0a7774d..bf02b0f70827 100644
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>---- llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp.orig
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+++ llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-@@ -15,6 +15,7 @@
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #include "llvm/ADT/APInt.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #include "llvm/ADT/STLExtras.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #include "llvm/ADT/SmallVector.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+#include "llvm/ADT/Triple.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #include "llvm/Analysis/InstructionSimplify.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #include "llvm/Analysis/ValueTracking.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #include "llvm/IR/Constant.h"
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-@@ -1324,10 +1325,13 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- return BinaryOperator::CreateSRem(RHS, NewRHS);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- }
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- }
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- // A+B --> A|B iff A and B have no bits set in common.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- return BinaryOperator::CreateOr(LHS, RHS);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ // Disable this transformation for ISPC SPIR-V
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ // A+B --> A|B iff A and B have no bits set in common.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ return BinaryOperator::CreateOr(LHS, RHS);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ }
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- // FIXME: We already did a check for ConstantInt RHS above this.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- // FIXME: Is this pattern covered by another fold? No regression tests fail on
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/11_0_11_1_packed_load_store_avx512.patch b/lang/ispc/files/11_0_11_1_packed_load_store_avx512.patch
</span>deleted file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index ac8b6648607..00000000000
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/lang/ispc/files/11_0_11_1_packed_load_store_avx512.patch
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -1,86 +0,0 @@
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-# This patch is required for llvm.expandload/compressstore intrinsiscs to work
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-# correctly for i64 types on avx512skx-i32x8
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Commit a4124e455e641db1e18d4221d2dacb31953fd13b Mon Sep 17 00:00:00 2001
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Author: Craig Topper <craig.topper@sifive.com>
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Date: Thu, 12 Nov 2020 20:18:50 -0800
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Subject: [X86] When storing v1i1/v2i1/v4i1 to memory, make sure we store zeros
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- in the rest of the byte
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-We can't store garbage in the unused bits. It possible that something like zextload from i1/i2/i4 is created to read the memory. Those zextloads would be legalized assuming the extra bits are 0.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-I'm not sure that the code in lowerStore is executed for the v1i1/v2i1/v4i1 case. It looks like the DAG combine in combineStore may have converted them to v8i1 first. And I think we're missing some cases to avoid going to the stack in the first place. But I don't have time to investigate those things at the moment so I wanted to focus on the correctness issue.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Should fix PR48147.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Reviewed By: RKSimon
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-Differential Revision: https://reviews.llvm.org/D91294
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-index 5b0e9fa7535..f1956d77d61 100644
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>---- llvm/lib/Target/X86/X86ISelLowering.cpp.orig
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+++ llvm/lib/Target/X86/X86ISelLowering.cpp
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-@@ -23870,17 +23870,22 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- // Without AVX512DQ, we need to use a scalar type for v2i1/v4i1/v8i1 stores.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- if (StoredVal.getValueType().isVector() &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal.getValueType().getVectorElementType() == MVT::i1) {
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- assert(StoredVal.getValueType().getVectorNumElements() <= 8 &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- "Unexpected VT");
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ unsigned NumElts = StoredVal.getValueType().getVectorNumElements();
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ assert(NumElts <= 8 && "Unexpected VT");
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- assert(!St->isTruncatingStore() && "Expected non-truncating store");
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- assert(Subtarget.hasAVX512() && !Subtarget.hasDQI() &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- "Expected AVX512F without AVX512DQI");
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ // We must pad with zeros to ensure we store zeroes to any unused bits.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1,
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- DAG.getUNDEF(MVT::v16i1), StoredVal,
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- DAG.getIntPtrConstant(0, dl));
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal = DAG.getBitcast(MVT::i16, StoredVal);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, StoredVal);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ // Make sure we store zeros in the extra bits.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ if (NumElts < 8)
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ StoredVal = DAG.getZeroExtendInReg(StoredVal, dl,
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ MVT::getIntegerVT(NumElts));
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- St->getPointerInfo(), St->getOriginalAlign(),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-@@ -44971,17 +44976,21 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal.getOpcode() == ISD::SCALAR_TO_VECTOR &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal.getOperand(0).getValueType() == MVT::i8) {
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- return DAG.getStore(St->getChain(), dl, StoredVal.getOperand(0),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ SDValue Val = StoredVal.getOperand(0);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ // We must store zeros to the unused bits.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ return DAG.getStore(St->getChain(), dl, Val,
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- St->getBasePtr(), St->getPointerInfo(),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- St->getOriginalAlign(),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- St->getMemOperand()->getFlags());
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- }
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- // Widen v2i1/v4i1 stores to v8i1.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- if ((VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- Subtarget.hasAVX512()) {
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- unsigned NumConcats = 8 / VT.getVectorNumElements();
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- SmallVector<SDValue, 4> Ops(NumConcats, DAG.getUNDEF(VT));
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ // We must store zeros to the unused bits.
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+ SmallVector<SDValue, 4> Ops(NumConcats, DAG.getConstant(0, dl, VT));
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- Ops[0] = StoredVal;
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-index 3d8fbdc3b82..339fd001643 100644
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>---- llvm/lib/Target/X86/X86InstrAVX512.td.orig
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+++ llvm/lib/Target/X86/X86InstrAVX512.td
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-@@ -2921,9 +2921,6 @@ def : Pat<(i64 (bitconvert (v64i1 VK64:$src))),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- // Load/store kreg
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- let Predicates = [HasDQI] in {
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- def : Pat<(store VK1:$src, addr:$dst),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK8))>;
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- def : Pat<(v1i1 (load addr:$src)),
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- (COPY_TO_REGCLASS (KMOVBkm addr:$src), VK1)>;
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- def : Pat<(v2i1 (load addr:$src)),
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/14_0_15_0_disable-DIArgList-in-SPIR-V.patch b/lang/ispc/files/14_0_15_0_disable-DIArgList-in-SPIR-V.patch
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..30e78ee396c
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/files/14_0_15_0_disable-DIArgList-in-SPIR-V.patch
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,25 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# This patch is needed for ISPC for Xe only
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# It disables using of DIArgList for dbg.val if SPIR-V target is used.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# It is needed till DIArgList is supported in SPIR-V Translator.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 1c350a258..55f783643 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Transforms/Utils/Local.cpp.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Transforms/Utils/Local.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -1798,7 +1798,16 @@ void llvm::salvageDebugInfoForDbgValues(
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ } else if (isa<DbgValueInst>(DII) && IsValidSalvageExpr &&
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ DII->getNumVariableLocationOps() + AdditionalValues.size() <=
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ MaxDebugArgs) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- DII->addVariableLocationOps(AdditionalValues, SalvagedExpr);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ DII->addVariableLocationOps(AdditionalValues, SalvagedExpr);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ } else {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // Do not salvage using DIArgList for dbg.addr/dbg.declare, as it is
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // currently only valid for stack value expressions.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // Also do not salvage if the resulting DIArgList would contain an
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // unreasonably large number of values.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Value *Undef = UndefValue::get(I.getOperand(0)->getType());
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ DII->replaceVariableLocationOp(I.getOperand(0), Undef);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ } else {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Do not salvage using DIArgList for dbg.addr/dbg.declare, as it is
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // currently only valid for stack value expressions.
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/14_0_AVX512VP2INTERSECT.patch b/lang/ispc/files/14_0_AVX512VP2INTERSECT.patch
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..3ad638e243e
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/files/14_0_AVX512VP2INTERSECT.patch
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,41 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# This is backport of commit bd5722b87b5aa, which removes VP2INTERSECT for SPR.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 10f9692d217e..2a00e58e000c 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Support/X86TargetParser.cpp.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Support/X86TargetParser.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -203,10 +203,10 @@ constexpr FeatureBitset FeaturesTigerlake =
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ constexpr FeatureBitset FeaturesSapphireRapids =
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ FeatureWAITPKG;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Intel Atom processors.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Bonnell has feature parity with Core2 and adds MOVBE.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -366,7 +366,7 @@ constexpr ProcInfo Processors[] = {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Tigerlake microarchitecture based processors.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Sapphire Rapids microarchitecture based processors.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Alderlake microarchitecture based processors.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Knights Landing processor.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index bafba2ee09c3..9b6e0fe06583 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Target/X86/X86.td.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Target/X86/X86.td
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -858,7 +858,6 @@ def ProcessorFeatures {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureTSXLDTRK,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureENQCMD,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureSHSTK,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- FeatureVP2INTERSECT,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureMOVDIRI,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureMOVDIR64B,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ FeatureUINTR];
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/14_0_fp16_converts.partial.fix.patch b/lang/ispc/files/14_0_fp16_converts.partial.fix.patch
</span>new file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index 00000000000..34dffff091f
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--- /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/lang/ispc/files/14_0_fp16_converts.partial.fix.patch
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -0,0 +1,104 @@
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# Backport of commit 6a6c527ee287 (available in 17.0). To avoid merge conflicts the whole function was copied from patch LLVM 15.0.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+# It enables better code geneartion for FP16 convert on SPR: int64/uint64 -> half (vcvtqq2ph / vcvtuqq2ph) for x8 target.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+index 8bb7e81e19bb..049c68b7cc3d 100644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+--- llvm/lib/Target/X86/X86ISelLowering.cpp.orig
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++++ llvm/lib/Target/X86/X86ISelLowering.cpp
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -53682,22 +53682,56 @@ static SDValue combineFP_ROUND(SDNode *N, SelectionDAG &DAG,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ if (!Subtarget.hasF16C() || Subtarget.useSoftFloat())
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return SDValue();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- if (Subtarget.hasFP16())
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- return SDValue();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+-
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ bool IsStrict = N->isStrictFPOpcode();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ EVT VT = N->getValueType(0);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- SDValue Src = N->getOperand(0);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Src = N->getOperand(IsStrict ? 1 : 0);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ EVT SrcVT = Src.getValueType();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ if (!VT.isVector() || VT.getVectorElementType() != MVT::f16 ||
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ SrcVT.getVectorElementType() != MVT::f32)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return SDValue();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDLoc dl(N);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Cvt, Chain;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ unsigned NumElts = VT.getVectorNumElements();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- if (NumElts == 1 || !isPowerOf2_32(NumElts))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (Subtarget.hasFP16()) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // Combine (v8f16 fp_round(concat_vectors(v4f32 (xint_to_fp v4i64), ..)))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ // into (v8f16 vector_shuffle(v8f16 (CVTXI2P v4i64), ..))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (NumElts == 8 && Src.getOpcode() == ISD::CONCAT_VECTORS) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Cvt0, Cvt1;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Op0 = Src.getOperand(0);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Op1 = Src.getOperand(1);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ bool IsOp0Strict = Op0->isStrictFPOpcode();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (Op0.getOpcode() != Op1.getOpcode() ||
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Op0.getOperand(IsOp0Strict ? 1 : 0).getValueType() != MVT::v4i64 ||
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Op1.getOperand(IsOp0Strict ? 1 : 0).getValueType() != MVT::v4i64) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return SDValue();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ int Mask[8] = {0, 1, 2, 3, 8, 9, 10, 11};
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (IsStrict) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ assert(IsOp0Strict && "Op0 must be strict node");
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ unsigned Opc = Op0.getOpcode() == ISD::STRICT_SINT_TO_FP
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ ? X86ISD::STRICT_CVTSI2P
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ : X86ISD::STRICT_CVTUI2P;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt0 = DAG.getNode(Opc, dl, {MVT::v8f16, MVT::Other},
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ {Op0.getOperand(0), Op0.getOperand(1)});
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt1 = DAG.getNode(Opc, dl, {MVT::v8f16, MVT::Other},
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ {Op1.getOperand(0), Op1.getOperand(1)});
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt = DAG.getVectorShuffle(MVT::v8f16, dl, Cvt0, Cvt1, Mask);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return DAG.getMergeValues({Cvt, Cvt0.getValue(1)}, dl);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ unsigned Opc = Op0.getOpcode() == ISD::SINT_TO_FP ? X86ISD::CVTSI2P
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ : X86ISD::CVTUI2P;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt0 = DAG.getNode(Opc, dl, MVT::v8f16, Op0.getOperand(0));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt1 = DAG.getNode(Opc, dl, MVT::v8f16, Op1.getOperand(0));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return Cvt = DAG.getVectorShuffle(MVT::v8f16, dl, Cvt0, Cvt1, Mask);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ return SDValue();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- SDLoc dl(N);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (NumElts == 1 || !isPowerOf2_32(NumElts))
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return SDValue();
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Widen to at least 4 input elements.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ if (NumElts < 4)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -53705,10 +53739,16 @@ static SDValue combineFP_ROUND(SDNode *N, SelectionDAG &DAG,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ DAG.getConstantFP(0.0, dl, SrcVT));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Destination is v8i16 with at least 8 elements.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- EVT CvtVT = EVT::getVectorVT(*DAG.getContext(), MVT::i16,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- std::max(8U, NumElts));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- SDValue Cvt = DAG.getNode(X86ISD::CVTPS2PH, dl, CvtVT, Src,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- DAG.getTargetConstant(4, dl, MVT::i32));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ EVT CvtVT =
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ EVT::getVectorVT(*DAG.getContext(), MVT::i16, std::max(8U, NumElts));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ SDValue Rnd = DAG.getTargetConstant(4, dl, MVT::i32);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (IsStrict) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt = DAG.getNode(X86ISD::STRICT_CVTPS2PH, dl, {CvtVT, MVT::Other},
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ {N->getOperand(0), Src, Rnd});
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Chain = Cvt.getValue(1);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ } else {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt = DAG.getNode(X86ISD::CVTPS2PH, dl, CvtVT, Src, Rnd);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ // Extract down to real number of elements.
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ if (NumElts < 8) {
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+@@ -53717,7 +53757,12 @@ static SDValue combineFP_ROUND(SDNode *N, SelectionDAG &DAG,
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ DAG.getIntPtrConstant(0, dl));
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+- return DAG.getBitcast(VT, Cvt);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ Cvt = DAG.getBitcast(VT, Cvt);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ if (IsStrict)
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return DAG.getMergeValues({Cvt, Chain}, dl);
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>++ return Cvt;
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ }
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+ static SDValue combineMOVDQ2Q(SDNode *N, SelectionDAG &DAG) {
</span><span style='display:block; white-space:pre;color:#808080;'>diff --git a/lang/ispc/files/patch-CMakeLists.txt.diff b/lang/ispc/files/patch-CMakeLists.txt.diff
</span>deleted file mode 100644
<span style='display:block; white-space:pre;color:#808080;'>index b178223865c..00000000000
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/lang/ispc/files/patch-CMakeLists.txt.diff
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ /dev/null
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -1,17 +0,0 @@
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>---- CMakeLists.txt.orig 2019-08-16 06:18:07.000000000 +0900
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+++ CMakeLists.txt 2019-10-13 12:27:19.000000000 +0900
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-@@ -35,10 +35,10 @@
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- #
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- cmake_minimum_required(VERSION 3.12)
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--if (UNIX)
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- set(CMAKE_C_COMPILER "clang")
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-- set(CMAKE_CXX_COMPILER "clang++")
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>--endif()
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+#if (UNIX)
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+# set(CMAKE_C_COMPILER "clang")
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+# set(CMAKE_CXX_COMPILER "clang++")
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-+#endif()
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- set(PROJECT_NAME ispc)
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>- set(ISPC_BUILD TRUE)
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