<pre style='margin:0'>
Perry E. Metzger (pmetzger) pushed a commit to branch master
in repository macports-ports.

</pre>
<p><a href="https://github.com/macports/macports-ports/commit/049b8b7ac9f2a0e70ebda109ce695b5d1dfc1185">https://github.com/macports/macports-ports/commit/049b8b7ac9f2a0e70ebda109ce695b5d1dfc1185</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'>     new 049b8b7ac9f verilator: update from 5.018 to 5.020
</span>049b8b7ac9f is described below

<span style='display:block; white-space:pre;color:#808000;'>commit 049b8b7ac9f2a0e70ebda109ce695b5d1dfc1185
</span>Author: Kenneth Østby <kenneth.ostby@gmail.com>
AuthorDate: Mon Jan 1 21:39:37 2024 -0800

<span style='display:block; white-space:pre;color:#404040;'>    verilator: update from 5.018 to 5.020
</span><span style='display:block; white-space:pre;color:#404040;'>    
</span><span style='display:block; white-space:pre;color:#404040;'>    * Updated verilator to 5.020
</span>---
 science/verilator/Portfile | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

<span style='display:block; white-space:pre;color:#808080;'>diff --git a/science/verilator/Portfile b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index 82810dea5bf..3c865d96aaf 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -3,7 +3,7 @@
</span> PortSystem              1.0
 PortGroup               github 1.0
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-github.setup            verilator verilator 5.018 v
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+github.setup            verilator verilator 5.020 v
</span> revision                0
 categories              science electronics
 license                 {LGPL-3 Artistic-2}
<span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -12,9 +12,9 @@ platforms               darwin
</span> description             Verilog compiler and simulator
 long_description        Verilator is a {*}${description}.
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-checksums               rmd160  05154dade12df2664a87e774bf49ac7121a8f80d \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        sha256  804e3affb9c6f80c97c02ce9fc58a4c79e6fdfcacadd8f8e27374428a6dd42da \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        size    3457342
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums               rmd160  026dd626ba18f76b269dfbfb78c58433803991e4 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        sha256  4d998f624b7d546ca18f811ade6b14c4e9e73b7f5cc6090ff173d45f8ec86508 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        size    3526644
</span> 
 compiler.cxx_standard   2014
 
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