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Renee Otten (reneeotten) pushed a commit to branch master
in repository macports-ports.

</pre>
<p><a href="https://github.com/macports/macports-ports/commit/8cf4900b80b75fe2100595b21930692a119d8ce1">https://github.com/macports/macports-ports/commit/8cf4900b80b75fe2100595b21930692a119d8ce1</a></p>
<pre style="white-space: pre; background: #F8F8F8">The following commit(s) were added to refs/heads/master by this push:
<span style='display:block; white-space:pre;color:#404040;'>     new 8cf4900b80b verilator: update to 5.028
</span>8cf4900b80b is described below

<span style='display:block; white-space:pre;color:#808000;'>commit 8cf4900b80b75fe2100595b21930692a119d8ce1
</span>Author: Jack Koenig <koenig@sifive.com>
AuthorDate: Wed Sep 11 17:57:20 2024 +0100

<span style='display:block; white-space:pre;color:#404040;'>    verilator: update to 5.028
</span>---
 science/verilator/Portfile | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

<span style='display:block; white-space:pre;color:#808080;'>diff --git a/science/verilator/Portfile b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;color:#808080;'>index 3c865d96aaf..989964801c8 100644
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>--- a/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0ff;'>+++ b/science/verilator/Portfile
</span><span style='display:block; white-space:pre;background:#e0e0e0;'>@@ -3,18 +3,17 @@
</span> PortSystem              1.0
 PortGroup               github 1.0
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-github.setup            verilator verilator 5.020 v
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+github.setup            verilator verilator 5.028 v
</span> revision                0
 categories              science electronics
 license                 {LGPL-3 Artistic-2}
 maintainers             {mcalhoun @MarcusCalhoun-Lopez} openmaintainer
<span style='display:block; white-space:pre;background:#ffe0e0;'>-platforms               darwin
</span> description             Verilog compiler and simulator
 long_description        Verilator is a {*}${description}.
 
<span style='display:block; white-space:pre;background:#ffe0e0;'>-checksums               rmd160  026dd626ba18f76b269dfbfb78c58433803991e4 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        sha256  4d998f624b7d546ca18f811ade6b14c4e9e73b7f5cc6090ff173d45f8ec86508 \
</span><span style='display:block; white-space:pre;background:#ffe0e0;'>-                        size    3526644
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+checksums               rmd160  5d45fa63999302629f90488b340470fa6a619b73 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        sha256  45d7381a1e3f7bcb3bd7117950490c9d870c1ad7a75dc61abf6245c98b1fc4c1 \
</span><span style='display:block; white-space:pre;background:#e0ffe0;'>+                        size    32548221
</span> 
 compiler.cxx_standard   2014
 
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