<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">And this article describes SIMDe:<div class=""><br class=""></div><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span><a href="https://simd-everywhere.github.io/blog/2020/06/22/transitioning-to-arm-with-simde.html" class="">https://simd-everywhere.github.io/blog/2020/06/22/transitioning-to-arm-with-simde.html</a><br class=""><div><br class=""></div></div><blockquote style="margin: 0 0 0 40px; border: none; padding: 0px;" class=""><div class=""><div><span style="caret-color: rgb(17, 17, 17); color: rgb(17, 17, 17); background-color: rgb(253, 253, 253);" class="">SIMD Everywhere (SIMDe) provides fast, portable, permissively-licensed (MIT) implementations of the x86 APIs which allow you to run code designed for x86/x86_64 CPUs pretty much anywhere, including on Arm (using NEON if available). With almost no source code changes, you can recompile your x86 SIMD code for Arm (or POWER, or WebAssembly, etc.).</span></div></div></blockquote><div class=""><div><br class=""></div><div>...that is not yet packaged for MacPorts ;-) ;-) ;-)</div><div><br class=""></div><div>G.</div><div><br class=""><blockquote type="cite" class=""><div class="">Le 26 avr. 2021 à 20:56, Georges Martin <<a href="mailto:jrjsmrtn@gmail.com" class="">jrjsmrtn@gmail.com</a>> a écrit :</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html; charset=utf-8" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><blockquote type="cite" class=""><div dir="ltr" class=""><div class="">Aha, hw.optional! That's useful, thanks Georges!</div></div></blockquote><div class=""><br class=""></div>You're welcome :-) You also have:<div class=""><br class=""></div><div class=""><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span>hw.optional.amx_version: 2</div><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span>hw.optional.arm64: 1</div><div class=""><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span>hw.targettype: J313</div></div><div class=""><br class=""></div><div class="">"amx" is the Neural Engine and I think "J313" is the code name for the M1.</div><div class=""><br class=""></div><div class="">You may find this article very interesting:</div><div class=""><br class=""></div><div class=""><span class="Apple-tab-span" style="white-space:pre"> </span><a href="https://levelup.gitconnected.com/armv9-what-is-the-big-deal-4528f20f78f3" class="">https://levelup.gitconnected.com/armv9-what-is-the-big-deal-4528f20f78f3</a></div><div class=""><br class=""></div><div class="">It describes the new ARMv9 instruction set with SVE2 and how it compares to Intel/AMD MMX/SSE/AVX and NEON/SVE.</div><div class=""><br class=""></div><div class="">Question is: would Apple adopt ARMv9 with SVE2 in a M2 for a future Mac Pro ? ;-)</div><div class=""><br class=""></div><div class="">G.</div><div class=""><br class=""><blockquote type="cite" class=""><div class="">Le 26 avr. 2021 à 20:44, Jason Liu <<a href="mailto:jasonliu@umich.edu" class="">jasonliu@umich.edu</a>> a écrit :</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div class="">Aha, hw.optional! That's useful, thanks Georges!</div><div class=""><br class=""></div><div class=""><div class=""><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr" class=""><div class="">-- </div><div class="">Jason Liu<br class=""></div></div></div></div><br class=""></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Apr 26, 2021 at 2:16 PM Georges Martin <<a href="mailto:jrjsmrtn@gmail.com" class="">jrjsmrtn@gmail.com</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div style="overflow-wrap: break-word;" class=""><div class="">$ sysctl hw.optional | grep -E 'neon|armv8'</div><div class="">hw.optional.neon: 1</div><div class="">hw.optional.neon_hpfp: 1</div><div class="">hw.optional.neon_fp16: 1</div><div class="">hw.optional.armv8_1_atomics: 1</div><div class="">hw.optional.armv8_crc32: 1</div><div class="">hw.optional.armv8_2_fhm: 1</div><div class="">hw.optional.armv8_2_sha512: 1</div><div class="">hw.optional.armv8_2_sha3: 1</div><div class=""><br class=""><blockquote type="cite" class=""><div class="">Le 26 avr. 2021 à 19:55, Jason Liu <<a href="mailto:jasonliu@umich.edu" target="_blank" class="">jasonliu@umich.edu</a>> a écrit :</div><br class=""><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div class=""><div dir="ltr" class="gmail_attr">On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones <<a href="mailto:jonesc@hep.phy.cam.ac.uk" target="_blank" class="">jonesc@hep.phy.cam.ac.uk</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class="">Thats not at all surprising as those instruction sets are very much specific to X86_64 systems.<div class=""><br class=""></div><div class="">RISC processors, Arm, do have their own sets of SIMD instructions (e.g. Neon), but they are entirely different to those on X86_64 machines. </div><div class=""><br class=""></div><div class="">Whether or these are supported on Apple’s M1 processors I have no idea.</div></div></blockquote></div><div class=""><br class=""></div><div class="">It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD (which I guess is supposed to be similar to AVX?):</div><div class=""><br class=""></div><div class=""><a href="https://discussions.apple.com/thread/252073619" target="_blank" class="">https://discussions.apple.com/thread/252073619</a></div><div class=""><br class=""></div><div class=""><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div class="">-- </div><div class="">Jason Liu<br class=""></div></div></div></div><br class=""></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones <<a href="mailto:jonesc@hep.phy.cam.ac.uk" target="_blank" class="">jonesc@hep.phy.cam.ac.uk</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div class=""><br class=""><div class=""><br class=""><blockquote type="cite" class=""><div class="">On 26 Apr 2021, at 6:28 pm, Jason Liu <<a href="mailto:jasonliu@umich.edu" target="_blank" class="">jasonliu@umich.edu</a>> wrote:</div><br class=""><div class=""><div dir="ltr" class=""><div class="">Thanks Arno :)</div><div class=""><br class=""></div><div class="">I'm kind of surprised that the M1 doesn't seem to support any SSE or AVX....</div></div></div></blockquote><div class=""><br class=""></div><div class=""><br class=""></div>Thats not at all surprising as those instruction sets are very much specific to X86_64 systems.</div><div class=""><br class=""></div><div class="">RISC processors, Arm, do have their own sets of SIMD instructions (e.g. Neon), but they are entirely different to those on X86_64 machines. </div><div class=""><br class=""></div><div class="">Whether or these are supported on Apple’s M1 processors I have no idea.</div><div class=""><br class=""></div><div class="">Chris</div><div class=""><br class=""></div><div class=""><br class=""></div><div class=""><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div class=""><br class=""></div><div class="">Does "sysctl machdep.cpu.features" return anything?<br class=""></div><div class=""><br class=""></div><div class=""><div class=""><div dir="ltr" class=""><div dir="ltr" class=""><div class="">-- </div><div class="">Jason Liu<br class=""></div></div></div></div><br class=""></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala <<a href="mailto:arno@alum.wpi.edu" target="_blank" class="">arno@alum.wpi.edu</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">> On 26 Apr 2021, at 13:20, Jason Liu <<a href="mailto:jasonliu@umich.edu" target="_blank" class="">jasonliu@umich.edu</a>> wrote:<br class="">
> <br class="">
> sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”<br class="">
<br class="">
$ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i "avx\|sse”<br class="">
machdep.cpu.brand_string: Apple M1<br class="">
<br class="">
-- <br class="">
arno s hautala /-| <a href="mailto:arno@alum.wpi.edu" target="_blank" class="">arno@alum.wpi.edu</a><br class="">
<br class="">
pgp b2c9d448<br class="">
<br class="">
<br class="">
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