[88223] trunk/dports/science/iverilog/Portfile

[ryandesign at macports.org]

Revision: 88223
          http://trac.macports.org/changeset/88223
Author:   ryandesign at macports.org
Date:     2011-12-22 02:42:02 -0800 (Thu, 22 Dec 2011)
Log Message:
-----------
iverilog: adjust whitespace and formatting

Modified Paths:
--------------
    trunk/dports/science/iverilog/Portfile

Modified: trunk/dports/science/iverilog/Portfile
===================================================================
--- trunk/dports/science/iverilog/Portfile	2011-12-22 10:40:02 UTC (rev 88222)
+++ trunk/dports/science/iverilog/Portfile	2011-12-22 10:42:02 UTC (rev 88223)
@@ -1,41 +1,43 @@
 # -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4
 # $Id$
 
-PortSystem 1.0
-name             iverilog
+PortSystem          1.0
+
+name                iverilog
 version             0.9.5
-set branch       [join [lrange [split ${version} .] 0 1] .]
-categories       science
-maintainers      nomaintainer
-description      Icarus Verilog
-long_description \
-    Icarus Verilog is a Verilog simulation and synthesis tool. It \
-    operates as a compiler, compiling source code writen in Verilog \
-    (IEEE-1364) into some target format. For batch simulation, the \
-    compiler can generate C++ code that is compiled and linked with \
-    a run time library (called \"vvm\") then executed as a command to \
-    run the simulation. For synthesis, the compiler generates netlists \
-    in the desired format.
-platforms        darwin
+set branch          [join [lrange [split ${version} .] 0 1] .]
+categories          science
+platforms           darwin
+maintainers         nomaintainer
 
+description         Icarus Verilog
+
+long_description    Icarus Verilog is a Verilog simulation and synthesis tool. \
+                    It operates as a compiler, compiling source code writen in \
+                    Verilog (IEEE-1364) into some target format. For batch \
+                    simulation, the compiler can generate C++ code that is \
+                    compiled and linked with a run time library (called \
+                    \"vvm\") then executed as a command to run the simulation. \
+                    For synthesis, the compiler generates netlists in the \
+                    desired format.
+
 homepage            http://iverilog.icarus.com/
-master_sites     ftp://ftp.icarus.com/pub/eda/verilog/v${branch}/
-distname         verilog-${version}
+master_sites        ftp://ftp.icarus.com/pub/eda/verilog/v${branch}/
+distname            verilog-${version}
 
 checksums           rmd160  5f7e60a92d1e1327e1c8fbd0c9a9045b5397ba39 \
                     sha256  c522b8b873f0cf77003db15c3df0f4a15b738ce4b060d1ca387c88e1b2be185d
 
-depends_lib      port:bzip2 \
-                 port:readline \
-                 port:zlib
+depends_lib         port:bzip2 \
+                    port:readline \
+                    port:zlib
 
-configure.args   mandir=\\\${prefix}/share/man
-destroot.destdir prefix=${destroot}${prefix}
+configure.args      mandir=\\\${prefix}/share/man
 
-platform darwin 8 {
-    depends_build-append    port:bison
-}
+test.run            yes
+test.target         check
 
+destroot.destdir    prefix=${destroot}${prefix}
 
 post-destroot {
     set docdir ${destroot}${prefix}/share/doc/${name}
@@ -54,12 +56,13 @@
     file rename ${exampledir}/examples ${exampledir}/${name}
 }
 
+platform darwin 8 {
+    depends_build-append    port:bison
+}
+
 # g++-4.2: -E, -S, -save-temps and -M options are not allowed with multiple -arch flags
-universal_variant no
+universal_variant   no
 
-test.run         yes
-test.target      check
-
-livecheck.type  regex
-livecheck.url   ${master_sites}
-livecheck.regex "verilog-(\\d+(?:\\.\\d+)*)${extract.suffix}"
+livecheck.type      regex
+livecheck.url       ${master_sites}
+livecheck.regex     "verilog-(\\d+(?:\\.\\d+)*)${extract.suffix}"
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