[MacPorts] #51642: GCC does not honor -march=native
MacPorts
noreply at macports.org
Wed Jun 15 20:52:56 PDT 2016
#51642: GCC does not honor -march=native
------------------------+--------------------------------
Reporter: noloader@… | Owner: macports-tickets@…
Type: defect | Status: new
Priority: Normal | Milestone:
Component: ports | Version: 2.3.4
Keywords: | Port:
------------------------+--------------------------------
I'm attempting a compile uder MacPort's GCC compiler:
{{{
$ make CXX=/opt/local//bin/x86_64-apple-darwin12-gcc-4.9.3
/opt/local//bin/x86_64-apple-darwin12-gcc-4.9.3 -DNDEBUG -g2 -O2 -fPIC
-march=native -pipe -c cryptlib.cpp
:1057:no such instruction: `vzeroupper'
:1507:no such instruction: `vzeroupper'
:1517:no such instruction: `vzeroupper'
:1662:no such instruction: `vzeroupper'
:1838:no such instruction: `vzeroupper'
...
}}}
Piping it into `wc` reveals:
{{{
$ make CXX=/opt/local//bin/x86_64-apple-darwin12-gcc-4.9.3 2>&1 | wc -l
190
}}}
The machine is a 2012 MacBook Pro with a Core i7-2760QM. Broadly speaking,
the cpu includes SSE4 and AES-NI, but lacks RDRAND and RDSEED:
{{{
$ sysctl -a | grep machdep.cpu.features
machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE
MCA CMOV PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 SS HTT TM PBE SSE3
PCLMULQDQ DTES64 MON DSCPL VMX SMX EST TM2 SSSE3 CX16 TPR PDCM SSE4.1
SSE4.2 x2APIC POPCNT AES PCID XSAVE OSXSAVE TSCTMR AVX1.0
}}}
`vzeroupper` is part of AVX, and AVX is available in the cpu feature set.
We have users who use a few MacPorts compilers, so I'm guessing additional
testing will reveal the same issue under GCC 5.1 and 5.3. I'm only going
to file this one report, however.
-----
Here's some additional information that may be useful.
{{{
$ port version
Version: 2.3.4
}}}
And:
{{{
$ sysctl -a | grep machdep.cpu
machdep.cpu.max_basic: 13
machdep.cpu.max_ext: 2147483656
machdep.cpu.vendor: GenuineIntel
machdep.cpu.brand_string: Intel(R) Core(TM) i7-2760QM CPU @ 2.40GHz
machdep.cpu.family: 6
machdep.cpu.model: 42
machdep.cpu.extmodel: 2
machdep.cpu.extfamily: 0
machdep.cpu.stepping: 7
machdep.cpu.feature_bits: 3219913727 532341759
machdep.cpu.extfeature_bits: 672139520 1
machdep.cpu.signature: 132775
machdep.cpu.brand: 0
machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE
MCA CMOV PAT PSE36 CLFSH DS ACPI MMX FXSR SSE SSE2 SS HTT TM PBE SSE3
PCLMULQDQ DTES64 MON DSCPL VMX SMX EST TM2 SSSE3 CX16 TPR PDCM SSE4.1
SSE4.2 x2APIC POPCNT AES PCID XSAVE OSXSAVE TSCTMR AVX1.0
machdep.cpu.extfeatures: SYSCALL XD EM64T LAHF RDTSCP TSCI
machdep.cpu.logical_per_package: 16
machdep.cpu.cores_per_package: 8
machdep.cpu.microcode_version: 26
machdep.cpu.processor_flag: 4
machdep.cpu.mwait.linesize_min: 64
machdep.cpu.mwait.linesize_max: 64
machdep.cpu.mwait.extensions: 3
machdep.cpu.mwait.sub_Cstates: 135456
machdep.cpu.thermal.sensor: 1
machdep.cpu.thermal.dynamic_acceleration: 1
machdep.cpu.thermal.invariant_APIC_timer: 1
machdep.cpu.thermal.thresholds: 2
machdep.cpu.thermal.ACNT_MCNT: 1
machdep.cpu.thermal.core_power_limits: 1
machdep.cpu.thermal.fine_grain_clock_mod: 1
machdep.cpu.thermal.package_thermal_intr: 1
machdep.cpu.thermal.hardware_feedback: 0
machdep.cpu.thermal.energy_policy: 0
machdep.cpu.xsave.extended_state: 7 832 832 0
machdep.cpu.arch_perf.version: 3
machdep.cpu.arch_perf.number: 4
machdep.cpu.arch_perf.width: 48
machdep.cpu.arch_perf.events_number: 7
machdep.cpu.arch_perf.events: 0
machdep.cpu.arch_perf.fixed_number: 3
machdep.cpu.arch_perf.fixed_width: 48
machdep.cpu.cache.linesize: 64
machdep.cpu.cache.L2_associativity: 8
machdep.cpu.cache.size: 256
machdep.cpu.tlb.inst.small: 64
machdep.cpu.tlb.inst.large: 8
machdep.cpu.tlb.data.small: 64
machdep.cpu.tlb.data.large: 32
machdep.cpu.tlb.shared: 512
machdep.cpu.address_bits.physical: 36
machdep.cpu.address_bits.virtual: 48
machdep.cpu.core_count: 4
machdep.cpu.thread_count: 8
}}}
--
Ticket URL: <https://trac.macports.org/ticket/51642>
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