M1 CPU features

[Jason Liu]

On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones <jonesc at hep.phy.cam.ac.uk>
wrote:

> Thats not at all surprising as those instruction sets are very much
> specific to X86_64 systems.
>
> RISC processors, Arm, do have their own sets of SIMD instructions (e.g.
> Neon), but they are entirely different to those on X86_64 machines.
>
> Whether or these are supported on Apple’s M1 processors I have no idea.
>

It looks like the M1 supports Neon SIMD instructions, but not SVE SIMD
(which I guess is supposed to be similar to AVX?):

https://discussions.apple.com/thread/252073619

-- 
Jason Liu


On Mon, Apr 26, 2021 at 1:42 PM Christopher Jones <jonesc at hep.phy.cam.ac.uk>
wrote:

>
>
> On 26 Apr 2021, at 6:28 pm, Jason Liu <jasonliu at umich.edu> wrote:
>
> Thanks Arno :)
>
> I'm kind of surprised that the M1 doesn't seem to support any SSE or
> AVX....
>
>
>
> Thats not at all surprising as those instruction sets are very much
> specific to X86_64 systems.
>
> RISC processors, Arm, do have their own sets of SIMD instructions (e.g.
> Neon), but they are entirely different to those on X86_64 machines.
>
> Whether or these are supported on Apple’s M1 processors I have no idea.
>
> Chris
>
>
>
>
> Does "sysctl machdep.cpu.features" return anything?
>
> --
> Jason Liu
>
>
> On Mon, Apr 26, 2021 at 1:23 PM Arno Hautala <arno at alum.wpi.edu> wrote:
>
>> > On 26 Apr 2021, at 13:20, Jason Liu <jasonliu at umich.edu> wrote:
>> >
>> > sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i
>> "avx\|sse”
>>
>> $ sysctl machdep.cpu.brand_string ; sysctl machdep.cpu | grep -i
>> "avx\|sse”
>> machdep.cpu.brand_string: Apple M1
>>
>> --
>> arno  s  hautala    /-|   arno at alum.wpi.edu
>>
>> pgp b2c9d448
>>
>>
>>
>
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